This invention relates to the data processing systems and, more particularly, to a data processing information storage and communication system for accomodating a very high speed memory.
A significant advance in computer system architecture has been the utilization of a unified bus. With unified bussing architecture, all devices, including the central processor, are connected in parallel to the bus. Any device (except memory) can dynamically request control of the bus to transfer information to another device using an approach based on real and simulated memory addresses. Thus, the central processor can look on its peripherals as if they were locations in memory with special properties and can operate on them using the same set of instructions used to operate on memory.
Devices communicate on the unified bus in a master-slave relationship. During any bus operation, one device has control of the bus. The device in control, called the master, communicates with another device called the slave. The relationship is dynamic such that, for example, the central processor as master may send control information to a disk (slave) which then could obtain the bus as a master to communicate with core memory as a slave.
The unified bus is used by the central processor and all input/output devices. A priority structure determines which device has control of the bus at any given instant of time. Therefore, every device capable of becoming bus master has an assigned priority, and when two devices request the bus at the same time, the device with the higher priority will receive control first. Communication on the unified bus is asynchronous and interlocked between devices. For each control signal issued by the master, there is a response from the slave; thus, communications is independent of physical bus length and the response time of master and slave devices.
However, even though unified bussing has been successful in increasing system generality, the advent of very high speed semiconductor memories (i.e., with access times which are less than bus transfer times) required a new approach to memory organization.
It is therefore a broad object of this invention to provide means for integrating a very high speed memory into a computer system utilizing unified bus architecture.
It is another object of this invention to provide a high speed memory subsystem which can communicate directly with a central processor unit, as a constituent thereof, and also with a bus in a unified bus computer system.
It is a more specific object of this invention to provide a high speed memory subsystem including control means for communicating within a central processor unit through a high speed dedicated bus and with other elements of the computer system as a parallel unit on a unified bus.